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Semiconductor
MSM514260E
262,144-Word x 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE
This version:Aug.2000
DESCRIPTION
The MSM514260E is a 262,144-word x 16-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MSM514260E achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/double-layer metal CMOS process. The MSM514260E is available in a 40-pin plastic SOJ, 44/40-pin plastic TSOP.
FEATURES
* * *
* * *
262,144-word x 16-bit configuration Single 5V power supply, 10% tolerance Input
Output Refresh
: TTL compatible, low input capacitance
: TTL compatible, 3-state : 512 cycles/8 ms
Fast page mode, read modify write capability
*
*
CAS before RAS refresh, hidden refresh, RAS-only refresh capability
Package options:
40-pin 400mil plastic SOJ 44/40-pin 400mil plastic TSOP
(SOJ40-P-400-1.27) (TSOPII44/40-P-400-0.80-K)
(Product : MSM514260E-xxJS) (Product : MSM514260E-xxTS-K) xx : indicates speed rank.
PRODUCT FAMILY
Family Access Time (Max.) tRAC 60ns 70ns tAA 30ns 35ns tCAC 15ns 20ns tOEA 15ns 20ns Cycle Time (Min.) 110ns 130ns Power Dissipation Operating (Max.) 633mW 578mW Standby (Max.) 5.5mW
MSM514260E
1/14
MSM514260E
PIN CONFIGRATION (TOP VIEW)
VCC 1 DQ1 2 DQ2 3 DQ3 4 DQ4 5 VCC 6 DQ5 7 DQ6 8 DQ7 9 DQ8 10 NC 11 NC 12 WE 13 RAS 14 NC 15 A0 16 A1 17 A2 18 A3 19 VCC 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VSS DQ16 DQ15 DQ14 DQ13 VSS DQ12 DQ11 DQ10 DQ9 NC LCAS UCAS OE A8 A7 A6 A5 A4 VSS
VCC 1 DQ1 2 DQ2 3 DQ3 4 DQ4 5 VCC 6 DQ5 7 DQ6 8 DQ7 9 DQ8 10 NC 13 NC 14 WE 15 RAS 16 NC 17 A0 18 A1 19 A2 20 A3 21 VCC 22
44 43 42 41 40 39 38 37 36 35 32 31 30 29 28 27 26 25 24 23
VSS DQ16 DQ15 DQ14 DQ13 VSS DQ12 DQ11 DQ10 DQ9 NC LCAS UCAS OE A8 A7 A6 A5 A4 VSS
40-Pin Plastic SOJ
44/40-Pin Plastic TSOP (K Type)
Pin Name A0 - A8 RAS LCAS UCAS DQ1 - DQ16 OE WE VCC VSS NC
Function Address Input Row Address Strobe Lower Byte Column Address Strobe Upper Byte Column Address Strobe Data Input/Data Output Output Enable Write Enable Power Supply (5V) Ground (0V) No Connection
Note : The same power supply voltage must be provided to every V CC pin, and the same GND voltage level must be provided to every VSS pin.
2/14
MSM514260E
BLOCK DIAGRAM
WE RAS LCAS UCAS
Column Address Buffers Internal Address Counter Row Address Buffers Timing Generator I/O Controller I/O Controller 9 9 Column Decoders 8 Output Buffers 8
OE
DQ1 - DQ8
8 I/O Selector Input Buffers 8
A0 - A8
Refresh Control Clock
Sense Amplifiers
16
16 Input Buffers
8 9 9 Row Decoders Word Drivers Memory Cells 8
8
DQ9 - DQ16
Output Buffers 8
VCC
On Chip VBB Generator
VSS
FUNCTION TABLE
Input Pin RAS H L L L L L L L L LCAS * H L H L L H L L UCAS * H H L L H L L L WE * * H H H L L L H OE * * L L L H H H H DQ Pin DQ1-DQ8 High-Z High-Z DOUT High-Z DOUT DIN Don't Care DIN High-Z DQ9-DQ16 High-Z High-Z High-Z DOUT DOUT Don't Care DIN DIN High-Z Function Mode Standby Refresh Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write
* : "H" or "L"
3/14
MSM514260E
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Voltage on Any Pin Relative to VSS Voltage VCC supply Relative to VSS Short Circuit Output Current Power Dissipation Operating Temperature Storage Temperature Symbol VIN, VOUT VCC IOS PD* Topr Tstg Rating -0.5 to VCC + 0.5 -0.5 to 7.0 50 1 0 to 70 -55 to 150 Unit V V mA W C C
*: Ta = 25C
Recommended Operating Conditions
(Ta = 0C to 70C)
Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol Min. 4.5 0 2.4 -0.5
*2
Typ. 5.0 0
Max. 5.5 0
Unit V V V V
VCC VSS VIH VIL
VCC + 0.5*1
0.8
Notes:
*1. The input voltage is VCC + 2.0V when the pulse width is less than 20ns (the pulse width is with respect to the point at which VCC is applied). *2. The input voltage is VSS - 2.0V when the pulse width is less than 20ns (the pulse width respect to the point at which VSS is applied).
Capacitance
(VCC = 5V 10%, Ta = 25C, f=1MHz)
Parameter Input Capacitance (A0 - A8) Input Capacitance (RAS, LCAS, UCAS, WE, OE) Output Capacitance (DQ1 - DQ16) Symbol Typ. Max. 5 7 7 Unit pF pF pF
CIN1 CIN2 CI/O
4/14
MSM514260E
DC Characteristics
(VCC = 5V 10%, Ta = 0C to 70C)
MSM514260 E-60 Min. Output High Voltage Output Low Voltage VOH VOL ILI IOH = -5.0mA IOL = 4.2mA 0V VI 6.5V ; Input Leakage Current All other pins not under test = 0V DQ disable 0V VO VCC RAS, CAS cycling, tRC = Min. RAS, CAS = VIH ICC2 RAS, CAS VCC - 0.2V RAS cycling, ICC3 CAS = VIH, tRC = Min. RAS = VIH, ICC5 CAS = VIL, DQ = enable Average Power Supply Current (CAS before RAS Refresh) Average Power Supply Current (Fast Page Mode) ICC6 RAS = cycling, CAS before RAS RAS = VIL, ICC7 CAS cycling, tPC = Min. 115 105 mA 1,3 115 105 mA 1,2 5 5 mA 1 115 105 mA 1,2 -10 10 -10 10 A 2.4 0 Max . VCC 0.4 MSM514260 E-70 Min. 2.4 0 Max . VCC 0.4
Parameter
Symbol
Condition
Unit
Note
V V
Output Leakage Current Average Power Supply Current (Operating) Power Supply Current (Standby)
ILO
-10
10
-10
10
A
ICC1

115 2 1

105 2
mA
1,2
mA 1
1
Average Power Supply Current (RAS-only Refresh)
Power Supply Current (Standby)
Notes: 1. 2. 3.
ICC Max. is specified as ICC for output open condition. The address can be changed once or less while RAS = VIL. The address can be changed once or less while CAS = VIH.
5/14
MSM514260E
AC Characteristic (1/2)
(VCC = 5V 10%, Ta = 0C to 70C) Note1,2,3
MSM514260 E-60 Min. Random Read or Write Cycle Time Read Modify Write Cycle Time Fast Page Mode Cycle Time Fast Page Mode Read Modify Write Cycle Time Access Time from RAS Access Time from CAS Access Time from Column Address Access Time from CAS Precharge Access Time from OE Output Low Impedance Time from CAS CAS to Data Output Buffer Turn-off Delay Time OE to Data Output Buffer Turn-off Delay Time Transition Time Refresh Period RAS Precharge Time RAS Pulse Width RAS Pulse Width (Fast Page Mode) RAS Hold Time RAS Hold Time referenced to OE CAS Precharge Time (Fast Page Mode) CAS Pulse Width CAS Hold Time CAS to RAS Precharge Time RAS Hold Time from CAS Precharge RAS to CAS Delay Time RAS to Column Address Delay Time Row Address Set-up Time Row Address Hold Time Column Address Set-up Time Column Address Hold Time tRC tRWC tPC tPRWC tRAC tCAC tAA tCPA tOEA tCLZ tOFF tOEZ tT tREF tRP tRAS tRASP tRSH tROH tCP tCAS tCSH tCRP tRHCP tRCD tRAD tASR tRAH tASC tCAH 110 155 40 85 0 0 0 3 40 60 60 15 15 10 15 60 5 35 20 15 0 10 0 10 Max. 60 15 30 35 15 15 15 50 8 10,000 100,000 10,000 45 30 MSM514260 E-70 Min. 130 185 45 100 0 0 0 3 50 70 70 20 20 10 20 70 5 40 20 15 0 10 0 15 Max. 70 20 35 40 20 15 15 50 8 10,000 100,000 10,000 50 35 ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 11 11 12 12 5 6 14 4,5,6 4,5 4,6 4,12 4 4 7 7 3
Parameter
Symbol
Unit
Note
6/14
MSM514260E
AC Characteristic (2/2)
(VCC = 5V 10%, Ta = 0C to 70C) Note1,2,3
MSM514260 E-60 Min. Column Address to RAS Lead Time Read Command Set-up Time Read Command Hold Time Read Command Hold Time referenced to RAS Write Command Set-up Time Write Command Hold Time Write Command Pulse Width OE Command Hold Time Write Command to RAS Lead Time Write Command to CAS Lead Time Data-in Set-up Time Data-in Hold Time OE to Data-in Delay Time CAS to WE Delay Time Column Address to WE Delay Time RAS to WE Delay Time CAS Precharge WE Delay Time CAS Active Delay Time from RAS Precharge RAS to CAS Set-up Time (CAS before RAS) RAS to CAS Hold Time (CAS before RAS) tRAL tRCS tRCH tRRH tWCS tWCH tWP tOEH tRWL tCWL tDS tDH tOED tCWD tAWD tRWD tCPWD tRPC tCSR tCHR 30 0 0 0 0 10 10 15 15 15 0 10 15 40 55 85 60 5 10 10 Max. MSM514260 E-70 Min. 35 0 0 0 0 15 10 20 20 20 0 15 20 50 65 100 70 5 10 10 Max. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 9 9 9 9 11 11 12 13 10,11 10,11 11 8,11 8 9,11 11
Parameter
Symbol
Unit
Note
7/14
MSM514260E
Notes:
1.
A start-up delay of 200s is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. The AC characteristics assume tT = 5ns. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. This parameter is measured with a load circuit equivalent to 2 TTL load and 100pF. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified t RCD (Max.) limit, then the access time is controlled by tCAC. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If t RAD is greater than the specified t RAD (Max.) limit, then the access time is controlled by tAA. tOFF (Max.) and tOEZ (Max.) define the time at which the output achieved the open circuit condition and are not referenced to output voltage levels. tRCH or tRRH must be satisfied for a read cycle. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS tWCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD tCWD (Min.), tRWD tRWD(Min.), t AWD tAWD (Min.) and t CPWD tCPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate.
2. 3.
4. 5.
6.
7.
8. 9.
10. These parameters are referenced to the UCAS and LCAS, leading edges in an early write cycle, and to the WE leading edge in an OE control write cycle, or a read modify write cycle. 11. These parameters are determined by the falling edge of either UCAS or LCAS, whichever is earlier. 12. These parameters are determined by the rising edge of either UCAS or LCAS, whichever is later. 13. tCWL should be satisfied by both UCAS and LCAS. 14. tCP is determined by the time both UCAS and LCAS are high.
8/14
MSM514260E
Timing Chart
* Read Cycle
tRC tRAS tRP tCRP tCSH tRCD tRAD tRAL tASR tRAH tASC
Column
RAS
VIH VIL
CAS
VIH VIL
tRSH tCAS
tCRP
tCAH
Address
VIH VIL VIH VIL VIH VIL
Row
tRCS tAA tROH tOEA tCAC tRAC
tRRH tRCH
WE
OE
tOEZ tCLZ
Valid Data-out
tOFF
DQ
VOH VOL
Open
"H" or "L" * Write Cycle (Early Write)
RAS
VIH VIL tCRP tRCD tRAD
tRC tRAS tRP tCSH tRSH tCAS tRAL tCRP
CAS
VIH VIL tASR
tRAH
tASC
tCAH
Column
Address
VIH VIL
Row
tCWL tWCS tWP tWCH
WE
VIH VIL VIH VIL VIH VIL
tRWL
OE
tDS
Valid Data-in
tDH
Open
DQ
"H" or "L"
9/14
MSM514260E * Read Modify Write Cycle
tRWC RAS VIH VIL tCRP CAS VIH VIL tASR Address VIH VIL tRAD tRAH tASC
Column
tRAS tRP tCSH tRCD tRSH tCAS tCWL tRWL tCRP
tCAH
Row
tRCS tRWD
tCWD
tWP
WE
VIH VIL VIH VIL tRAC tCLZ tCAC tOEZ
Valid Data-out
tAWD tAA tOEA tOED tDS
Valid Data-in
tOEH
OE
tDH
DQ
VI/OH VI/OL
"H" or "L"
10/14
MSM514260E * Fast Page Mode Read Cycle
tRASP RAS VIH VIL tCRP CAS VIH VIL tASR Address VIH VIL VIH VIL VIH VIL tRAC tCAC DQ VOH VOL tCLZ tCPA tOFF tOEZ
Valid Data-out
tRP tPC tRHCP tCP tCAS tRSH tCAS tRAL tASC
Column
tRCD tCAS tRAD tCSH tRAH tASC
tCP
tCRP
tCAH
tASC
tCAH
tCAH
Row
Column
Column
tRCS WE tAA
tRCH tAA tOEA
tRCS
tRCH tAA
tRCS
tRCH
tOEA tCPA tOFF tOEZ
Valid Data-out
tOEA
tRRH
OE
tCAC tCLZ
tCAC tCLZ tOEZ
Valid Data-out
tOFF
"H" or "L"
*
Fast Page Mode Write Cycle (Early Write)
tRASP RAS VIH VIL VIH VIL tASR Address VIH VIL
Row
tRP tPC tRHPC tCP tCAS tRSH tCAS tRAL tCAH
Column
tCRP
tRCD tCAS tRAD tRAH tASC tCSH tCAH
tCP
tCRP
CAS
tASC
tCAH
tASC
Column
Column
tWCS WE VIH VIL tDS DQ VIH VIL
tWCH tWP
tCWL tWCS
tCWL tWCH tWP tDH
Valid Data-in
tRWL tCWL tWCS tWP tWCH
tDH
Valid Data-in
tDS
tDS
Valid Data-in
tDH
Note: OE = "H" or "L"
"H" or "L"
11/14
MSM514260E * Fast Page Mode Read Modify Write Cycle
tRASP RAS VIH VIL VIH VIL tRAH tASR Address VIH VIL
Row
tCSH tRCD tRAD tASC
Column
tPRWC tCAS tCP tCAS tCAH tCAH tCWL tASC tCWL
Column Column
tRSH tCP tCAS tCAH tASC tCRP
tRP
CAS
tRAL
tRCS WE VIH VIL tRAC tAA
tPWD tCWD tAWD tWP tDH tDS tOEA
tRCS
tCPWD
tCWD tAWD tCPA tAA tOEA tOED tOEZ Out tCLZ In tCLZ tWP tDS tDH tAA
tRCS tCPWD tCWD tAWD tROH tCPA tOEA tOED tOEZ Out In
tCWL tRWL
tWP tDH tDS
OE
VIH VIL tCAC VI/OH VI/OL tCLZ
tOED tOEZ Out In tCAC
tCAC
DQ
Note: Out = Valid Data-out, In = Valid Data-in
"H" or "L"
*
RAS-only Refresh Cycle
tRC RAS VIH VIL tCRP CAS VIH VIL VIH VIL VOH VOL tASR tRAH tRPC tRAS tRP
Address
Row
tOFF
Open Note: WE, OE = "H" or "L"
DQ
"H" or "L"
12/14
MSM514260E * CAS before RAS Refresh Cycle
tRP RAS VIH VIL tRPC tCP tCSR tCHR tOFF DQ VOH VOL tRAS
tRC
tRP tRPC
CAS
VIH VIL
Open Note: WE, OE, Address = "H" or "L"
"H" or "L"
*
Hidden Refresh Read Cycle
tRC RAS VIH VIL VIH VIL tASR Address VIH VIL VIH VIL tRAL tAA tROH OE VIH VIL VOH VOL
Open
tRAS tCRP tRCD tRAD tRAH
Row
tRC tRAS tRSH tRP tCHR tRP
CAS
tASC
Column
tCAH
tRCS WE
tCAC
tRRH
tOFF
tOEA tRAC tCLZ
Valid Data-out "H" or "L"
tOEZ
DQ
13/14
MSM514260E Hidden Refresh Write Cycle
tRC RAS VIH VIL VIH VIL tASR Address VIH VIL VIH VIL VIH VIL VIH VIL tDS tDH tWP tRAD tRAH
Row
tRC tRAS tRSH tRP tCHR tRAL tRP
tRAS tCRP tRCD
CAS
tASC
Column
tCAH
tWCS WE
tWCH
OE
DQ
Valid Data-in "H" or "L"
14/14
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit and assembly designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. OKI assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to:traffic control, automotive, safety, aerospace, nuclear power control, and medical, including lift support and maintenance. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission.
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Copyright 1997 OKI ELECTRIC INDUSTRY CO.,LTD.

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